Digital oversampling of a serial bitstream is the first step of a commonly used method of recovering data from the bitstream that is asynchronous to locally available clocks. High-speed data transceivers, such as devices operating at 1 Gb/s and higher, are often implemented in integrated circuits to enable high speed data transmission. If a design requires using the data transceiver for lower-rate applications, such as interfacing with legacy systems, an oversampling circuit must be attached to the “back end” of the data transceiver to extend the data transceiver to the lower frequency ranges. The circuit works by oversampling the incoming serial data stream, evaluating data transition locations, and extracting valid data bits from the oversampled data. The oversampled data is then analyzed to locate bit boundaries and choose the optimal samples for recovery of each bit.
A programmable logic device (PLD), which is designed to be user-programmable so that users may implement logic designs of their choices, is one type of device which implements high speed interfaces and may require digital oversampling. Programmable logic circuits of a PLD generally comprise gates which are configurable by a user of the circuit to implement a circuit design of the user. One type of PLD is a Complex Programmable Logic Device (CPLD) which includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs), where the CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. The oversampling ratio of a circuit in a PLD is generally selectable during operation to facilitate multi-rate applications. A variety of methods for oversampling a serial bitstream may be implemented in conventional PLDs. For example, one common method is to create multiple phases of the sampling clock using one or more digital clock managers. Another common technique is to use high speed SERDES blocks as asynchronous digital sampling devices.
However, conventional circuits for enabling oversampling of a bitstream employ complex timing circuits, such as a digital clock manager (DCM) found in programmable logic devices. A DCM is a system-level clock manager that simultaneously enables internal and external clock de-skew, high-resolution phase adjustment, and flexible frequency synthesis. In particular, a DCM provides complete on-chip and off-chip clock generators, offering powerful clock management features including clock de-skew for generating clock signals which are phase-aligned to the input clock. The DCM also generates a wide range of output clock frequencies, performing very flexible clock multiplication and division. Finally, the DCM provides both coarse phase shifting and fine-grained phase shifting with dynamic phase shift control. While higher system bandwidth calls for high data rates between devices requiring advanced clock management systems, such complex circuitry of a digital clock manager is more complex and takes up more circuitry than should be necessary for providing oversampling of a signal in an integrated circuit.
Accordingly, there is a need for an improved method of and circuit for oversampling a signal in an integrated circuit.